Electronic calculator systems of the type wherein all of the main electronic functions are integrated in a single large cell integrated semiconductor chip or in a small number of such chips, are described in the following U.S. Patents, which are assigned the assignee of this invention:
U.S. Pat. No. 3,919,532 issued to Michael J. Cochran and Charles P. Grant on Nov. 11, 1975 and entitled "CALCULATOR SYSTEM HAVING AN EXCHANGE DATA MEMORY REGISTER".
U.S. Pat. No. 3,934,233 issued to Roger J. Fisher and Gerald D. Rogers on Jan. 20, 1976 and entitled "READ-ONLY-MEMORY FOR ELECTRONIC CALCULATOR".
U.S. Pat. No. 3,931,507 issued Jan. 6, 1976 to George L. Brantingham entitled "POWER-UP CLEAR IN AN ELECTRONIC DIGITAL CALCULATOR".
The concepts of these prior applications have made possible vast reductions in the cost of small personal-size calculators. Continuing efforts to reduce the cost of these products include the design of a single chip calculator system for use in large capacity calculators, such as scientific or business calculators. The chip disclosed herein may be utilized in scientific or business calculators for instance, because this chip has provisions for a number of storage registers, in addition to operational registers, as well as sufficient capacity to solve the more complicated mathematical expressions and functions used in scientific and business calculators including, for example, trigonometric and logarithmic relationships.
The present invention relates to a hexadecimal/binary coded decimal format arithmetic unit for a microprocessor and more specifically a hexadecimal/binary coded decimal format arithmetic unit for an electronic calculator. An entire eleccalculator system including the hexadecimal/binary coded decimal arithmetic unit of this invention is disclosed. The electronic calculator disclosed is a serial, word organized calculator; however, the arithmetic unit of this invention is not limited to the type calculator system disclosed. Electronic calculators of the prior art have typically been operable in a single mode, such as in binary coded decimal format. While such a single mode arithmetic unit may be well suited for use in performing normal arithmetic functions, it has been found that if the data being applied to the arithmetic unit represents, for instance, either the logical status of operations occurring within the calculator or binary coded decimal (BCD) numerals that having an arithmetic unit which automatically preforms the logical operations in binary coded decimal format complicates the interpretation or decoding of the such logical operations.
It is therefore one object of this invention to provide an arithmetic unit operable in a first mode for performing arithmetic operations in hexadecimal and operable in a second mode for performing arithmetic operations in binary coded decimal format. It is yet another object of this invention to provide a second mode of the arithmetic unit with capability to automatically and selectively preform arithmetic operations on BCD inputs in BCD format and to preform operations on flag bit inputs in hexidecimal, that is, equivalently the binary base.
The foregoing objects are achieved according to the present invention as is now described. In a preferred embodiment of the invention, a hexadecimal/BCD arithmetic unit is provided on a semiconductor chip preferably having an input circuit for receiving numeric data and function commands, an address register responsive to the input circuit, an instruction word memory for storing a number os instruction words and addressable in response to the address stored in the address register and instruction word decoder logic for decoding instruction words outputted from the instruction word memory and for controlling the arithmetic unit in response thereto. The arithmetic unit is provided with a binary/hexadecimal adder and a BCD corrector. The BCD corrector is disableable according to instruction words read out of the instruction memory or in accordance with timing signals generated on the chip which are indicative of whether the input to the arithmetic unit represents BCD data or flag bit information.